1. Field of the Invention
The present invention relates to an information processor, and more particularly, to an information processor being suited for processing large graph data.
2. Description of the Related Art
In an information processor, the response time to a data request in data processing can be shortened significantly by previously loading required data into memory having high response speed before the CPU (host system) of a computer performs data processing. Conventionally, in the case of shortening the response time for data access in data processing, a method has been used in which, while a host system performs data processing, the controller of a storage device transfers only the data to be requested next by the host system from a non-volatile memory inside the storage device to a cache memory inside the storage device beforehand (refer to JP-T-2009-539168 (Patent Document 1)).
When large data is processed, for example, when a large graph is processed, a host for performing graph processing is required to control a large memory space and to store large graph data in the memory space. Hence, a main memory being large and operating at high speed is required to process a large graph at high speed.
Hence, the inventors of the present application examined related art in which all the memory chips used in a main memory are DRAM chips and also examined a method in which such a storage device as disclosed in Patent Document 1 is used as a main memory.
In the related art in which all the memory chips used in a main memory are DRAM chips, the CPU of a host for performing graph processing first downloads graph data to be processed from an external storage device or creates a graph and stores the graph into DRAM chips disposed in a memory space. Hence, in the case that graph data being large in data size is processed, it is necessary to mount DRAM chips serving as a main memory to the extent that the total storage capacity of the DRAM chips is sufficient to store the graph data.
However, a graph processing system in which DRAM chips are mounted on a large scale is expensive.
For this reason, it is conceivable to employ a method in which memory chips more inexpensive than DRAM chips are used to build a graph processing system at low cost.
A large and inexpensive memory space can be provided by disposing such a storage device as disclosed in Patent Document 1 in a memory space. However, in the case that graph processing is performed at high speed, this method has the following problems.
In the case that such a storage device as disclosed in Patent Document 1 is disposed in a memory space and graph processing is performed, the CPU of a host for performing the graph processing first downloads the graph data to be processed from an external storage device or creates graph data and stores the graph data into the storage device disposed in the memory space.
Then, the CPU performs graph processing using the graph data stored inside the storage device. The controller of the storage device loads the data into the host and then transfers only the graph data to be required next from the non-volatile memory inside the storage device to the cache memory inside the storage device while the host system performs the graph processing.
However, since the storage device is disposed in the memory space, the host obtains the graph data to be required next in the graph processing from the cache memory of the CPU of the host in some cases. In this case, the graph data having been transferred beforehand by the controller of the storage device into the cache memory inside the storage device is not requested by the host. Hence, when data is requested from the host to the storage device next time, the requested data does not exist in the cache memory inside the storage device. For this reason, the data is required to be readout from the non-volatile memory inside the storage device and to be returned to the host.
Furthermore, even in the case that the data requested by the host to the storage device does not coincide with the data stored in the cache memory of the CPU of the host but coincides with the data having been transferred beforehand from the non-volatile memory inside the storage device to the cache memory inside the storage device, it is conceivable that the host results in requesting the data to the storage device before the graph data to be required next by the host is completely transferred from the non-volatile memory inside the storage device to the cache memory inside the storage device because the time for data processing performed by the host is generally short in graph processing. Hence, also in this case, the data is required to be readout from the non-volatile memory inside the storage device and to be returned to the host.
Since the time required for reading out data from the non-volatile memory is longer than the time required for reading out the data from the DRAM, in the case that such a technology as disclosed in Patent Document 1 is used, there arises a problem that the time required for subjecting the data to graph processing becomes very long.
As described above, in the information processor adopting the conventional technology, when a large graph is processed, there arises a problem that a memory space being inexpensive and large cannot be provided or high-speed access to graph data cannot be achieved.
Accordingly, an object of the present invention is to provide an information processor capable of solving the above-mentioned problems encountered in the conventional technology and having main memory being suited for large data processing, being low in cost and large in capacity, and operating at high speed.